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CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16
Integrated Device Technology, Inc.
IDT72105 IDT72115 IDT72125
FEATURES:
* * * * * * * * * 25ns parallel port access time, 35ns cycle time 45MHz serial output shift rate Wide x16 organization offering easy expansion Low power consumption (50mA typical) Least/Most Significant Bit first read selected by asserting the FL/DIR pin Four memory status flags: Empty, Full, Half-Full, and Almost-Empty/Almost-Full Dual-Port zero fall-through architecture Available in 28-pin 300 mil plastic DIP and 28-pin SOIC Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72105/72115/72125s are very high-speed, lowpower,dedicated, parallel-to-serial FIFOs. These FIFOs possess a 16-bit parallel input port and a serial output port with 256, 512 and 1K word depths, respectively. The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT's unique serial expansion logic makes this possible using a minimum of pins. The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset. Monitoring the FIFO is eased by the availability of four status flags: Empty, Full, Half-Full and Almost-Empty/AlmostFull. The Full and Empty flags prevent any FIFO data overflow or underflow conditions. The Half-Full Flag is available in both single and expansion mode configurations. The Almost-Empty/ Almost-Full Flag is available only in a single device mode. The IDT72105/15/25 are fabricated using IDT's leading edge, submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MilSTD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
RS W D0-15
16
RESET LOGIC WRITE POINTER RAM ARRAY 256 x 16 512 x 16 1024 x 16 READ POINTER
RSIX RSOX FL/DIR SERIAL OUTPUT LOGIC EXPANSION LOGIC FLAG LOGIC
FF EF HF AEF
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co.
SOCP
SO
2665 drw 01
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2665/6
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
W
D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P28-2 SO28-3
EF FF HF
Vcc D15 D 14 D13 D12 D11 D10 D9 D8
RS
RSIX GND
SO SOCP RSOX/AEF
FL/DIR
2665 drw 02a
DIP/SOIC TOP VIEW
PIN DESCRIPTIONS
Symbol D0-D15 Name Inputs Reset I/O I I Data inputs for 16-bit wide data. When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset. A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. This is a dual purpose input used in the width and depth expansion configurations. The First Load ( FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first device to be loaded with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first. In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX is connected to RSOX (expansion out) of the previous device. Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the Direction pin programming. During Expansion the SO pins are tied together. When FF goes LOW, the device is full and further WRITE operations are inhibited. When HIGH, the device is not full. When EF goes LOW, the device is empty and further READ operations are inhibited. When HIGH, the device is not empty. Description
RS W
SOCP
Write
I
Serial Output Clock First Load/ Direction
I I
FL/DIR
RSIX SO
Read Serial In Expansion Serial Output Full Flag Empty Flag Half-Full Flag
I O O O O O
FF EF HF
FF is EF is
When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to half-full. This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF output pin. When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When AEF is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the width, depth or daisy chain expansion. Single power supply of 5V. Single ground of 0V.
2665 tbl 01
RSOX/AEF Read Serial Out Expansion Almost-Empty, Almost-Full Flag VCC GND Power Supply Ground
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
STATUS FLAGS
Number of Words in FIFO IDT72105 0 1-31 32-128 129-224 225-255 256 IDT72115 0 1-63 64-256 257-448 449-511 512 IDT72125 0 1-127 128-512 513-896 897-1023 1024
FF
H H H H H L
AEF
L L H H L L
HF
H H H L L L
EF
L H H H H H
2665 tbl 02
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current
(1)
RECOMMENDED DC OPERATING CONDITIONS
Unit V
Commercial -0.5 to + 7.0 0 to +70 -55 to +125 -55 to + 125 50
Symbol VCC GND VIH VIL(1)
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage
Min. 4.5 0 2.0 --
Typ. 5.0 0 -- --
Max. 5.5 0 -- 0.8
Unit V V V V
2665 tbl 04
C C C
mA
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE: 2665 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial VCC = 5.0V 10%, TA = 0C to +70C)
IDT72105/IDT72115/ IDT72125 Commercial Symbol I
IL (1)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage I OUT = -2mA(5) Output Logic "0" Voltage IOUT = Power Supply Current Average Standby Current (W = RS = FL/DIR = VIH)(SOCP = VIL ) Power Down Current 8mA(6)
Min. -1 -10 2.4 -- -- -- --
Typ. -- -- -- -- 50 4 1
Max. 1 10 -- 0.4 100 8 6
Unit
A A
V V mA mA mA
2665 tbl 05
IOL(2) VOH VOL ICC1 (3) ICC2 (3) ICC3 (3,4,7)
NOTES: 1. Measurements with 0.4V VIN VCC. 2. SOCP = VIL, 0.4 VOUT VCC. 3. ICC measurements are made with outputs open. 4. RS = FL/DIR = W = VCC - 0.2V; SOCP = 0.2V; all other inputs VCC - 0.2 or 0.2V. 5. For SO, IOUT = -4mA. 6. For SO, IOUT = 16mA. 7. Measurements are made after reset.
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V10%, TA = 0C to +70C)
COM'L 72105L25 72115L25 72125L25 Symbol tS tSOCP tWC tWPW tWR tDS tDH tWEF tWFF tWF tWPF tSOCP tSOCW tSOPD tSOHZ tSOLZ tSOCEF tSOCFF tSOCF tREFSO tRSC tRS tRSS tRSR tFLS tFLH tDIRS tDIRH tSOXD1 tSOXD2 tSIXS tSIXPW Parameter Parallel Shift Frequency Serial Shift Frequency Write Cycle Time Write Pulse Width Write Recovery Time Data Set-up Time Data Hold Time Write Low to FF LOW Write High to EF HIGH Write Low to Transitioning HF, AEF Figure -- -- 2 2 2 2 2 5, 6 4, 7 8 7 3 3 3 3 3 5, 6 4, 7 8 6 1 1 1 1 9 9 9 9 9 9 9 9 Min. -- -- 35 25 10 12 0 -- -- -- 25 20 8 -- 3 3 -- -- -- 35 35 25 25 10 7 0 10 5 -- -- 5 10 Max. 28.5 50 -- -- -- -- -- 35 35 35 -- -- -- 14 14 14 35 35 35 -- -- -- -- -- -- -- -- -- 15 15 -- -- Min. -- -- 65 50 15 15 2 -- -- -- 50 25 10 -- 3 3 -- -- -- 65 65 50 50 15 8 2 12 5 -- -- 8 15 72105L50 72115L50 72125L50 Max. 15 40 -- -- -- -- -- 45 45 45 -- -- -- 15 15 15 45 45 45 -- -- -- -- -- -- -- -- -- 17 17 -- -- Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2665 tbl 06
PARALLEL INPUT TIMINGS
Write Pulse Width After FF HIGH Serial Clock Cycle Time Serial Clock Width HIGH/LOW
SERIAL OUTPUT TIMINGS
SOCP Rising Edge to SO Valid Data SOCP Rising Edge to SO at SOCP Rising Edge to SO at High-Z (1) Low-Z (1)
SOCP Rising Edge to EF LOW
SOCP Rising Edge to FF HIGH
SOCP Rising Edge to Transitioning SOCP Delay After EF HIGH Reset Cycle Time Reset Pulse Width Reset Set-up Time Reset Recovery Time
HF, AEF
RESET TIMINGS
EXPANSION MODE TIMINGS
FL Set-up Time to RS Rising Edge FL Hold Time to RS Rising Edge
DIR Set-up Time to SOCP Rising Edge DIR Hold Time from SOCP Rising Edge SOCP Rising Edge to RSOX Rising Edge SOCP Rising Edge to RSOX Falling Edge RSIX Set-up Time to SOCP Rising Edge RSIX Pulse Width
NOTE: 1. Values guaranteed by design.
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure A
2665 tbl 07
5V 1.1K TO OUTPUT PIN
680
30pF *
2665 drw 03
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT
NOTE:
Parameter(1) Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 12
Unit pF pF
2665 tbl 08
or equivalent circuit
Figure A. Output Load *Includes jig and scope capacitances.
1. This parameter is sampled and not 100% tested.
FUNCTIONAL DESCRIPTION
Parallel Data Input The device must be reset before beginning operation so that all flags are set to their initial state. In width or depth expansion the First Load pin (FL) must be programmed to indicate the first device. The data is written into the FIFO in parallel through the D0- 15 input data lines. A write cycle is initiated on the falling edge of the Write (W) signal provided the Full Flag (FF) is not asserted. If the W signal changes from HIGH-to-LOW and the Full Flag (FF) is already set, the write line is internally inhibited internally from incrementing the write pointer and no write operation occurs. Data set-up and hold times must be met with respect to the
rising edge of Write. On the rising edge of W, the write pointer is incremented. Write operations can occur simultaneously or asynchronously with read operations. Serial Data Output The serial data is output on the SO pin. The data is clocked out on the rising edge of SOCP providing the Empty Flag (EF) is not asserted. If the Empty Flag is asserted then the next data word is inhibited from moving to the output register and being clocked out by SOCP. The serial word is shifted out Least Significant Bit or Most Significant Bit first, depending on the FL/DIR level during operation. A LOW on DIR will cause the Least Significant Bit to be read out first. A HIGH on DIR will cause the Most Significant Bit to be read out first.
tRSC
tRS RS tRSS W tRSC AEF, EF tRSC HF, FF tRSS SOCP NOTE 2 tFLS FL/DIR
2665 drw 04
tRSR
FLAG STABLE FLAG STABLE tRSR
tFLH
NOTES: 1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC. 2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR. Figure 1. Reset
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
t WC t WPW W t WR
D 0-15 t DS
Figure 2. Write Operation
t DH
2665 drw 05
1/t SOCP 0 SOCP t SOCW SO
(First Device in Width Expansion Mode)
1 t SOCW
n-1
t SOHZ
SO
(Single Device Mode or Second Device in Width Expansion Mode)
t SOLZ t SOPD
2665 drw 06
NOTE: 1. In Single Device Mode, SO will not tri-state except after reset. Figure 3. Read Operation
LAST WRITE SOCP
IGNORED WRITE
FIRST READ 0 1 n-1
ADDITIONAL READS 0 1 n-1
FIRST WRITE
W t WFF FF
2665 drw 07
t SOCFF
Figure 4. Full Flag from Last Write to First Read
LAST READ W 0 SOCP t SOCEF EF t SOPD SO VALID 1 n-1
NO READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
0
NOTE 1
1
n-1
t SOCFF
VALID
VALID
2665 drw 08
NOTE: 1. SOCP should not be clocked until EF goes HIGH. Figure 5. Empty Flag from Last Read to First Write
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
DATA IN
W t WEF EF t SOCP NOTE 1 NOTE 2 SO
NOTE: 1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH. 2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data. Figure 6. Empty Boundary Condition Timing
REFSO
t SOCEF
0
1
n-1
t
SOLZ
t SOPD
2665 drw 09
0 SOCP t SOCFF FF
1
n-1
t WFF
t WPF W t DS DATA IN NOTE 1 SO t SOPD DATA OUT VALID
2665 drw 10
t DH
DATA IN VALID NOTE 1
NOTE: 1. Single Device Mode will not tri-state but will retain the last valid data. Figure 7. Full Boundary Condition Timing
W
HALF-FULL (1/2) HALF-FULL HALF-FULL + 1
HF t WF SOCP t WF AEF
7/8 FULL
t SOCF
t SOCF
ALMOST-FULL (7/8 FULL + 1) 7/8 FULL
AEF
ALMOST-EMPTY (1/8 FULL - 1)
1/8 FULL
ALMOST-EMPTY (1/8 FULL - 1)
2665 drw 11
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
RS 15 SOCP t FLS FL/DIR t SOXD1 RSOX t SIXS RSIX t RSIXPW
2665 drw 12
0
t FLH
t DIRS
t DIRH
t SOXD2
Figure 9. Serial Read Expansion
OPERATING CONFIGURATIONS
Single Device Mode The device must be reset before beginning operation so that all flags are set to location zero. In the standalone case, the RSIX line is tied HIGH and indicates single device operation to the device. The RSOX/AEF pin defaults to AEF and outputs the Almost-Empty and Almost-Full Flag.
Width Expansion Mode In the cascaded case, word widths of more than 16 bits can be achieved by using more than one device. By tying the RSOX and RSIX pins together, as shown in Figure 11, and programming which is the Least Significant Device, a cascaded serial word is achieved. The Least Significant Device is programmed by a LOW on the FL/DIR pin during reset. All other devices should be programmed HIGH on the FL/DIR pin at reset.
PARALLEL DATA IN
D 0-15 Vcc SERIAL OUTPUT CLOCK RSIX SOCP RSOX/AEF SO ALMOST-EMPTY/FULL FLAG SERIAL DATA OUT
2665 drw 13
Figure 10. Single Device Configuration
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
Inputs Mode Reset Read/Write
Internal Status DIR X 0,1 Read Pointer Location Zero Increment(1) Write Pointer Location Zero Increment(1)
Outputs
RS
0 1
FL
X X
AEF EF AEF,
0 X
FF
1 X
HF
1 X
2665 tbl 09
NOTE: 1. Pointer will increment if appropriate flag is HIGH. Table 1. Reset and First Load Truth Table-Single Device Configuration
The Serial Data Output (SO) of each device in the serial word must be tied together. Since the SO pin is three stated, only the device which is currently shifting out is enabled and driving the 1-bit bus. NOTE: After reset, the level on the FL/DIR pin decides if the Least Significant or Most Significant
PARALLEL DATA IN
Bit is read first out of each device. The three flag outputs, Empty (EF), Half-Full (HF) and Full (FF), should be taken from the Most Significant Device (in the example, FIFO #2). The Almost-Empty/Almost-Full flag is not available. The RSOX pin is used for expansion.
SERIAL OUTPUT CLOCK
LOW AT RESET D 0-15 W RSIX D 16-31 W RSIX
HIGH AT RESET
SOCP FIFO #1 RSOX
FL/DIR
EF HF
SOCP FIFO #2 RSOX
FL/DIR
EF HF
EMPTY FLAG HALF-FULL FLAG FULL FLAG
SO
FF
SO
FF
SERIAL DATA OUT
2665 drw 14
Figure 11. Width Expansion for 32-bit Parallel Data In
Depth Expansion (Daisy Chain) Mode The IDT72105/15/25 can easily be adapted to applications requiring greater than 1024 words. Figure 12 demonstrates Depth Expansion using three IDT72105/15/25s and an IDT74FCT138 Address Decoder. Any depth can be attained by adding additional devices. The Address Decoder is necessary to determine which FIFO is being written. A word of data must be written sequentially into each FIFO so that the data will be read in the correct sequence. The IDT72105/15/25 operates in the Depth Expansion Mode when the following conditions are met: 1. The first device must be programmed by holding FL LOW at Reset. All other devices must be programmed by holding FL HIGH at reset. 2. The Read Serial Out Expansion pin (RSOX) of each device must be tied to the Read Serial In Expansion pin (RSIX) of the next device (see Figure 12).
3. External logic is needed to generate composite Empty, Half-Full and Full Flags. This requires the OR-ing of all EF, HF and FF Flags. 4. The Almost-Empty and Almost-Full Flag is not available due to using the RSOX pin for expansion.
Compound Expansion (Daisy Chain) Mode The IDT72105/15/25 can be expanded in both depth and width as Figure 13 indicates: 1. The RSOX-to-RSIX expansion signals are wrapped around sequentially. 2. The write (W) signal is expanded in width. 3. Flag signals are only taken from the Most Significant Devices. 4. The Least Significant Device in the array must be programmed with a LOW on FL/DIR during reset.
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
LOW AT RESET PARALLEL DATA IN D 0-15 W SOCP ADDRESS 00 DECODER 01 74FCT138 10 D 0-15 W SERIAL OUTPUT CLOCK SOCP RSIX FIFO #2 RSOX SO
RSIX FIFO #1 RSOX
FL/DIR
EF HF
EMPTY FLAG
SO
FF
HIGH AT RESET
FL/DIR
EF HF FF HALF-FULL FLAG
HIGH AT RESET D 0-15 W SOCP
RSIX FIFO #3 RSOX
FL/DIR
EF HF FULL FLAG SERIAL DATA
OUT
SO
FF
2665 drw 15
Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125
Inputs Mode Reset-First Device Reset All Other Devices Read/Write
Internal Status DIR X X 0,1 Read Pointer Location Zero Location Zero X Write Pointer Location Zero Location Zero X
Outputs
RS
0 0 1
FL
0 1 X
EF
0 0 X
HF FF HF,
1 1 X
2665 tbl 10
NOTE: 1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output. Table 2. Reset and First Load Truth Table-Width/Depth Compound Expansion Mode
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
ADDRESS DECODER 74FCT138 PARALLEL DATAIN 00 01 10 SERIAL OUTPUT CLOCK LOW ON RESET HIGH ON RESET
SOCP D 0-15
FL/DIR
RSOX SO
EF HF FF
SOCP D16-31
FL/DIR
RSOX
FIFO #1
W
FIFO #2
RSIX
W
RSIX
SO
EF HF FF
EMPTY FLAG
SOCP D 0-15
FL/DIR
RSOX SO
FIFO #3
W
EF HF FF
SOCP D16-31
FL/DIR
RSOX SO
FIFO #4
RSIX
W
RSIX
EF HF FF
HALF-FULL FLAG
SOCP D 0-15
FL/DIR
RSOX SO
EF HF FF
SOCP D16-31
FL/DIR
RSOX
FIFO #5
W
FIFO #6
RSIX
W
RSIX
SO
EF HF FF
FULL FLAG SERIAL DATA
OUT
2665 drw 16
Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125
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IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type X Power X Speed X Package X Process/ Temperature Range BLANK Commercial (0C to +70C)
TP SO
Plastic THINDIP (300mil) Small Outline (Gull Wing)
25 50
(50 MHz serial shift rate) (40MHz serial shift rate)
Commercial only Parallel Access Time (tA) in ns
L 72105 72115 72125
Low Power 256 x 16-Bit Parallel-to-Serial FIFO 512 x 16-Bit Parallel-to-Serial FIFO 1024 x 16-Bit Parallel-to-Serial FIFO
2665 drw 17
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